The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a heterojunction field-effect transistor using a SiGeC or SiGe layer, and to a method of producing this semiconductor device.
Recently, high integration of a semiconductor device is under way. It is even intended to miniaturize a MOS transistor in which a gate length is below 0.1 xcexcm. In such ultra-miniaturization, however, the current driving ability is saturated due to the influence of a short channel effect or an increase in resistance component. Thus, there cannot be expected such improvements in performance that have hitherto been made. In particular, to increase the driving ability of a miniaturized MOS transistor, it is important to improve the mobility of carriers in a channel and to lower a source-drain electrode in contact resistance.
In view of the foregoing, there has been proposed, instead of a complementary semiconductor device (CMOS device) formed on a silicon substrate, a heterostructure CMOS device (hereinafter referred to as an HCMOS device) using Si/SiGe (mixed crystal of the IV-family elements). The HCMOS device utilizes, as a channel, the interface of a heterojunction structure of two kinds of semiconductors different in band gap from each other, instead of the Si/Sio2 interface. By using Si/SiGe capable of providing a carrier mobility higher than that provided by Si, it is expected to achieve a transistor higher in operational speed. By controlling the composition of Si/SiGe, it is possible to form, on a Si substrate, an epitaxial growth layer having the desired amount of strain and the desired value of band gap. Ismail of the IBM company has conducted basic experiments on improvements in characteristics of an HCMOS device of the Si/SiGe type (See K.Ismail, xe2x80x9cSi/SiGe High Speed Field-Effect Transistorsxe2x80x9d, IEDM Tech. Dig. 1995, p509 and M. A. Armstrong et al, xe2x80x9cDesign of Si/SiGe Heterojunction Complementary Metal-Oxide Semiconductor Transistorsxe2x80x9d, IEDM Tech. Dig. 1995, p761).
FIG. 15 is a section view of an example of this HCMOS device. As shown in FIG. 15, there is formed, on a portion of a Si substrate 101, a field-effect transistor comprising source-drain regions 109, a gate insulating layer 107 and a gate electrode 110. Formed in a so-called channel region between the source-drain regions under the gate electrode 110 are a SiGe buffer layer 102, a xcex4 doped layer 115, a spacer layer 103, an i-Si layer 104, an i-SiGe layer 105 and an i-Si layer 106. In these layers, the SiGe buffer layer 102 gives tensile strain to the i-Si layer 104 for forming an n-channel layer 112 between the SiGe buffer layer 102 and the i-Si layer 104. In the SiGe buffer layer 102, the Ge composition rate is gradually changed such that the Ge composition rate in that portion of the layer 102 immediately above the Si substrate 101 is equal to 0%, while the Ge composition rate in the top portion of the layer 102 is equal to 30%.
When a negative bias voltage is applied, the n-channel layer 112 is formed on the heterointerface between the i-Si layer 104 and the SiGe buffer layer 102 thereunder. The xcex4 doped layer 115 is arranged to supply electrons serving as carriers to the n-channel layer 112 which is formed on the xcex4 doped layer 115. The spacer layer 103 is arranged to spatially separate the ions in the xcex4 doped layer 115 formed below the spacer layer 103, from the n-channel layer 112 formed on the spacer layer 103, thus preventing the carrier mobility from being lowered due to ion scattering.
On the other hand, when a positive bias voltage is applied, a p-channel layer 111 is formed, at the side of the i-SiGe layer 105, on the heterointerface between the i-SiGe layer 105 and the i-Si layer 106 thereon. The gate insulating layer 107 is formed to insulate the gate electrode 110 from the p-channel layer 111.
As discussed in the foregoing, the heterojunction field-effect transistor is characterized in that a channel is formed on the heterointerface between two kinds of semiconductor layers different in band gap from each other. Accordingly, to form a channel, there are inevitably present at least two kinds of semiconductor layers different in band gap from each other. In addition, to form, in semiconductor layers, a channel in which electrons or positive holes move at a high speed, it is required to form, at the heterointerface, a discontinuous portion of a conduction or valence band. In the Si/SiGe type above-mentioned, the i-SiGe layer 105 has a discontinuous portion in the valence band with respect to the i-Si layer 106, thus forming a channel for positive holes (See the left portion of FIG. 15). However, the conduction band hardly has a discontinuous portion. Accordingly, tensile strain is induced in the i-Si layer 104 such that a discontinuous portion is formed in the conduction band at the heterointerface between i-Si layer 104 and the i-SiGe layer 105 (See the right portion of FIG. 15).
According to a simulation, it is estimated that, as compared with a conventional CMOS device in the same size using a Si/SiO2 channel, the HCMOS device having the arrangement above-mentioned achieves an operation at double the speed with a half power consumption. More specifically, this is a semiconductor transistor in which a Si semiconductor is combined with a SiGe mixed crystal to form a heterointerface and in which there is formed a channel in which carriers are mobile at a high speed. Thus, attention is placed to this semiconductor transistor as a transistor capable of achieving both a high-speed operation utilizing a heterojunction and large-scale integration of a MOS device.
A heterojunction device utilizing a mixed crystal of the IV-family elements such as SiGe is expected as means for overcoming the functional limit of a CMOS device of prior art. Due to the difficulty in production, however, a heterojunction field-effect transistor using a mixed crystal of the IV-family elements represented by SiGe is behind in research and development as compared with a heterojunction bipolar transistor which is a hetero device similarly using a mixed crystal such as SiGe. Thus, it cannot be stated that studies have sufficiently be made on the structure capable of providing performance as expected and on the method of producing such structure.
Further, in a heterojunction field-effect transistor having a so-called heterojunction MOS structure having an insulating layer between a gate electrode and a semiconductor layer as above-mentioned, a stable and good insulating layer cannot be formed in the SiGe layer. Accordingly, an oxide layer of SiO2 is used as a gate insulating layer. It is therefore required that a Si layer is always present immediately below the gate insulating layer. However, Si is characterized in that its band gap is always greater than the band gap of SiGe. This is disadvantageous in the above-mentioned HCMOS device of prior art as set forth below.
Firstly, to form an electron channel on the Si substrate 101, tensile strain is induced in the i-Si layer 104 to form a band discontinuous portion at the Si/SiGe heterointerface. However, the lattice constant undergoes a change to induce dislocation due to lattice relaxation.
FIG. 16 is a section view illustrating the SiGe buffer layer 102 and the i-Si layer 104 thereabove, as picked out from FIG. 15. Since the i-Si layer 104 is smaller in lattice constant than the SiGe buffer layer 102, tensile strain will be accumulated at the stage of crystal growth. When such accumulation becomes great, this results in dislocation in the i-Si layer 104 as shown in FIG. 16. Thus, dislocation or line defect is inevitably induced by strain due to lattice misfit between the i-Si layer 104 and the SiGe buffer layer 102. Setting apart from the initial characteristics of a transistor utilizing such a crystal, it is considered that the reliability and life-time of the transistor are influenced by the deterioration in characteristics due to the growth of dislocation in the crystal.
The SiGe buffer layer 102 made of SiGe greater in lattice constant than Si is laminated on the Si substrate 101 and tensile strain is accumulated in the i-Si layer 104 which is grown on the SiGe buffer layer 102. As the thickness of the SiGe buffer layer 102 is increased, the thickness exceeds the critical thickness in which the lattice constant of the SiGe buffer layer 102 is changed from the lattice constant of Si to the original lattice constant of SiGe. This produces lattice relaxation, causing defects such as dislocation or the like to be induced also in the SiGe buffer layer 102.
There are instances where such defects do not exert a significant influence on the initial characteristics of the transistor. In view of long-term reliability and life-time, however, such defects involve a possibility of a serious trouble being caused. More specifically, the transistor is deteriorated due to the growth of defects by an electric current or the diffusion of metal or impurity through the defects, thus possibly causing the transistor to be lowered in reliability.
Secondly, a heterojunction field-effect device using a mixed crystal of the IV-family elements represented by SiGe is effective as a transistor structure capable of overcoming the performance limit of a miniaturized CMOS device of prior art. At this point of time, however, studies on optimization of the contact of each source-drain electrode have not sufficiently been done as compared with studies on improvements in channel mobility. Thus, the structure cannot take full advantage of such high-speed mobility. In the IBM""s heterojunction CMOS device technology mentioned earlier, too, detailed studies have been made on improvements in mobility of a channel region, but studies have hardly been made on reduction in resistance of the contact of each source-drain electrode which is another important factor for improvement in performance of a miniaturized transistor.
More specifically, in a CMOS device structure using a single crystal of Si, a variety of studies have been made on the structure of the contact region of the substrate connected to a source-drain electrode. However, studies are required as to whether or not the contact region structure and its production method which are optimized for a general CMOS device, are also good for a heterojunction field-effect device different in transistor structure.
It is a first object of the present invention to provide a semiconductor device high in carrier mobility and reliability in which there is utilized, as a structure in a channel region under a gate of an HCMOS device, a heterojunction structure in lattice fit or substantially in lattice fit, yet having a band discontinuous portion where a carrier accumulation layer can be formed.
It is a second object of the present invention to provide a semiconductor device having contact regions low in contact resistance without excellent characteristics of a heterostructure field-effect device injured, and to provide a method of producing the semiconductor device above-mentioned.
To achieve the first object, the present invention provides a first semiconductor device, a second semiconductor device and a first semiconductor device producing method.
To achieve the second object, the present invention provides a third semiconductor device and a second semiconductor device producing method.
The first semiconductor device according to the present invention comprises a field-effect transistor which is formed on a portion of a semiconductor substrate and which comprises a gate electrode, source-drain regions and a channel region between the source-drain regions, and the channel region comprises: a Si layer; a Si1xe2x88x92xxe2x88x92yGexCy layer (0xe2x89xa6xxe2x89xa61, 0xe2x89xa6yxe2x89xa61) which is formed as coming in contact with the Si layer and in which the composition rate y of C is in the range from 0.01 to 0.03; and a carrier accumulation layer formed in that portion of the Si1xe2x88x92xxe2x88x92yGexCy layer which is adjacent to the Si layer.
At the interface between the Si layer and the Si1xe2x88x92xxe2x88x92yGexCy layer in which the composition rate y of C is in the range from 0.01 to 0.03, there can be formed a band discontinuous portion required for forming a carrier accumulation layer in which carriers are two-dimensionally confined. Since this carrier accumulation layer functions as a channel, there can be obtained a field-effect transistor high in operational speed in which the Si1xe2x88x92xxe2x88x92yGexCy layer giving a higher carrier mobility than in the Si layer, serves as a channel. Further, control can be made such that lattice misfit between the Si1xe2x88x92xxe2x88x92yGexCy layer and the Si layer does not occur or is minimized. It is therefore possible to make an adjustment such that lattice strain is not induced or substantially not induced. This enables the Si1xe2x88x92xxe2x88x92yGexCy layer to be formed with no crystal defect induced therein. Thus, a highly reliable semiconductor device can be obtained.
According to the present invention, the composition rates of the respective elements in the Si1xe2x88x92xxe2x88x92yGexCy layer may be adjusted such that the Si1xe2x88x92xxe2x88x92yGexCy layer and the Si layer are fitted in lattice for each other.
This enables a channel to be formed in the Si1xe2x88x92xxe2x88x92yGexCy layer free from strain due to lattice misfit. Thus, a highly reliable semiconductor device can be obtained.
According to the present invention, provision may be made such that the Si1xe2x88x92xxe2x88x92yGexCy layer has a lattice constant smaller than that of the Si layer and has such a thickness as to induce no lattice relaxation.
With the arrangement above-mentioned, tensile strain is induced in the Si1xe2x88x92xxe2x88x92yGexCy layer. This increases the amount of a band discontinuous portion with respect to the Si layer, thus enhancing the carrier confining efficiency.
According to the present invention, carriers accumulated in the carrier accumulation layer may be negative.
According to the present invention, a carrier supply layer for supplying carriers to the carrier accumulation layer is preferably formed in that portion of the Si layer which is adjacent to the Si1xe2x88x92xxe2x88x92yGexCy layer.
Preferably, the present invention is arranged such that carriers accumulated in the carrier accumulation layer are negative, that there is formed another field-effect transistor which is formed on other portion of the semiconductor substrate and which comprises a gate electrode, source-drain regions and a channel region between the source-drain regions, and that the channel region of another field-effect transistor comprises: a second Si layer; a SiGe layer formed adjacent to the second Si layer; and a second carrier accumulation layer for accumulating positive carriers, which is formed in that portion of the SiGe layer adjacent to the second Si layer.
With the arrangement above-mentioned, there can be obtained a semiconductor device functioning as an HCMOS device which assures a high carrier mobility in each of the n-channel and p-channel sides.
According to the present invention, the Si1xe2x88x92xxe2x88x92yGexCy or SiGe layer may be a quantum well region.
With the arrangement above-mentioned, there can be obtained a field-effect transistor having a channel high in carrier confining efficiency.
According to the present invention, each of the source-drain regions may comprise a first semiconductor layer and a second semiconductor layer greater in band gap than the first semiconductor layer, and there may further be formed source-drain contact layers each of which is made of a conductive layer low in resistance and each of which is formed immediately above the first semiconductor layer.
With the arrangement above-mentioned, a semiconductor device low in contact resistance can be obtained even with the use of a heterojunction structure.
The second semiconductor device according to the present invention comprises: a field-effect transistor which is formed on a portion of a semiconductor substrate and which comprises a gate electrode; source-drain regions; and a channel region between the source-drain regions, and the channel region comprises: a first Si layer; a first Si1xe2x88x92xxe2x88x92yGexCy layer (0xe2x89xa6xxe2x89xa61, 0 less than yxe2x89xa61) which is formed as coming in contact with the first Si layer; a second Si layer; a second Si1xe2x88x92xxe2x88x92yGexCy layer (0xe2x89xa6xxe2x89xa61, 0xe2x89xa6yxe2x89xa61) which is formed as coming in contact with the second Si layer and which is different in band gap from the first Si1xe2x88x92xxe2x88x92yGexCy layer; and first and second carrier accumulation layers for respectively confining different conductive carriers, these first and second carrier accumulation layers being respectively formed in that portion of the first Si1xe2x88x92xxe2x88x92yGexCy layer which is adjacent to the first Si layer and in that portion of the second Si1xe2x88x92xxe2x88x92yGexCy layer which is adjacent to the second Si layer.
According to the arrangement above-mentioned, there can be obtained a semiconductor device functioning as an HCMOS device having n-channel and p-channel field-effect transistors each having a channel high not only in carrier confining efficiency but also in operational speed. Further, control can be made such that lattice misfit between the first Si1xe2x88x92xxe2x88x92yGexCy layer and the first Si layer does not occur or is minimized. This enables the first Si1xe2x88x92xxe2x88x92yGexCy layer to be formed with no crystal defect induced therein. Thus, a highly reliable semiconductor device can be obtained.
According to the present invention, the composition rate y of C in the second Si1xe2x88x92xxe2x88x92yGexCy layer may be equal to 0.
According to the present invention, there may further be disposed a MOS transistor which is formed on the semiconductor substrate and in which a semiconductor layer formed of a single element serves as a channel region.
With the arrangement above-mentioned, a transistor provided in the channel region thereof with the first Si1xe2x88x92xxe2x88x92yGexCy layer may be used for a circuit requiring a high operational speed, and a usual MOS transistor may be used for other circuit, thus enabling the applicable range of the semiconductor device to be enlarged.
According to the present invention, provision may be made such that the first Si1xe2x88x92xxe2x88x92yGexCy layer has a lattice constant smaller than that of the first Si layer and has such a thickness as to induce no lattice relaxation.
With the arrangement above-mentioned, tensile strain is induced in the first Si1xe2x88x92xxe2x88x92yGexCy layer. This increases the amount of a band discontinuous portion with respect to the first Si layer, thus enhancing the carrier confining efficiency.
According to the present invention, a carrier supply layer for supplying carriers to the first carrier accumulation layer is preferably formed in that portion of the first Si layer which is adjacent to the first Si1xe2x88x92xxe2x88x92yGexCy layer.
The third semiconductor device according to the present invention comprises at least one field-effect transistor formed on a semiconductor substrate, and this field-effect transistor comprises: a channel region comprising a first semiconductor layer including a Si1xe2x88x92xxe2x88x92yGexCy layer (0xe2x89xa6xxe2x89xa61, 0xe2x89xa6yxe2x89xa61), a second semiconductor layer different in band gap from the first semiconductor layer, and a carrier accumulation layer formed in the vicinity of the interface between the first and second semiconductor layers; source-drain regions each comprising: a third semiconductor layer and a fourth semiconductor layer greater in band gap than the third semiconductor layer; and source-drain contact layers each of which is made of a conductive layer, each of which is low in resistance and each of which is formed immediately above the third semiconductor layer.
The arrangement above-mentioned can lower the resistance of a contact with respect to each source-drain region in the field-effect transistor high not only in carrier mobility but also in operational speed with the use of a heterojunction structure.
The present invention may be arranged such that the first semiconductor layer also serves as the third semiconductor layer, that the second semiconductor layer also serves as the fourth semiconductor layer, and that the second semiconductor layer is formed on the first semiconductor layer.
The present invention may be arranged such that the first and third semiconductor layers are respectively formed by different semiconductor layers, that the third semiconductor layer is formed on the first semiconductor layer, and that the fourth semiconductor layer is formed on the third semiconductor layer.
The first semiconductor device producing method according to the present invention, provides a method of producing a semiconductor device including an n-channel field-effect transistor and a p-channel field-effect transistor, and comprises: a first step of forming, on a semiconductor substrate, a first Si layer and a first Si1xe2x88x92xxe2x88x92yGexCy layer (0xe2x89xa6xxe2x89xa61, 0 less than yxe2x89xa61) which comes in contact with the first Si layer and in which a first carrier accumulation layer serving as a channel of the n-channel field-effect transistor is formed in that portion of the first Si1xe2x88x92xxe2x88x92yGexCy layer which is adjacent to the first Si layer; a second step of forming, on the semiconductor substrate, a second Si layer and a second Si1xe2x88x92xxe2x88x92yGexCy layer (0xe2x89xa6xxe2x89xa61, 0xe2x89xa6yxe2x89xa61) which comes in contact with the second Si layer, which is different in band gap from the first Si1xe2x88x92xxe2x88x92yGexCy layer and in which a second carrier accumulation layer serving as a channel of the p-channel field-effect transistor is formed in that portion of the second Si1xe2x88x92xxe2x88x92yGexCy layer which is adjacent to the second Si layer; a third step of depositing a conductive layer on the first or second Si1xe2x88x92xxe2x88x92yGexCy layer whichever is the upper, and patterning the conductive layer to form the gate electrodes of the n- and p-channel field-effect transistors; and a fourth step of introducing, with the gate electrodes of the field-effect transistors used as masks, (i) n-type impurity into the n-channel field-effect transistor forming region in depth which reaches at least the first carrier accumulation layer and (ii) p-type impurity into the p-channel field-effect transistor forming region in depth which reaches at least the second carrier accumulation layer, thus forming source-drain regions of the n- and p-channel field-effect transistors.
According to the method above-mentioned, the second semiconductor device of the present invention can readily be produced.
The second semiconductor device producing method of the present invention provides a method of producing a semiconductor device which has a first semiconductor layer including a Si1xe2x88x92xxe2x88x92yGexCy layer (0xe2x89xa6xxe2x89xa61, 0xe2x89xa6yxe2x89xa61), a second semiconductor layer different in band gap from the first semiconductor layer and a carrier accumulation layer serving as a channel formed in the vicinity of the interface between the first and second semiconductor layers, and which serves as a field-effect transistor, and this second semiconductor device method comprises: a first step of successively forming, on a field-effect transistor forming region of a semiconductor substrate, a third semiconductor layer and a fourth semiconductor layer greater in band gap than the third semiconductor layer; a second step of depositing a conductive layer on the fourth semiconductor layer and patterning the conductive layer to form a gate electrode; a third step of introducing impurity into those portions of the field-effect transistor forming region which are located at both lateral sides of the gate electrode, thus forming source-drain regions, the impurity being introduced in depth which reaches at least the carrier accumulation layer; a fourth step of etching the fourth semiconductor layer in the source-drain regions until at least the third semiconductor layer is exposed; and a fifth step of forming, on the exposed surface of the third semiconductor layer, source-drain contact layers made of conductive layers low in resistance.
According to the method above-mentioned, the third semiconductor device of the present invention can readily be produced.
According to the present invention, the fourth step is preferably executed under etching conditions in which the etching selectivity for the third and fourth semiconductor layers is high.